The present invention relates generally to semiconductor fabrication and more specifically to formation of flash memory floating gate oxide.
The most important electrical parameter of Flash memory is Forward Tunneling Voltage (FTV). FTV is a measurement of the ease of erasing the cell by removing the charge from F6xe2x86x92CG. The trap-up rate, i.e. electron (exe2x88x92) trapping in oxide, is also an important electrical parameter.
U.S. Pat. No. 6,031,264 B1 to Chien et al. describes a flash EEPROM process using polyoxide steps.
U.S. Pat. No. 5,879,993 to Chien et al. describes a flash EEPROM process.
U.S. Pat. No. 6,355,527 B1 to Lin et al. describes a flash EEPROM process.
U.S. Pat. Nos. 6,088,269 to Lambertson and 6,358,796 B1 to Lin et al. each describe related Flash processes.
Accordingly, it is an object of one or more embodiments of the present invention to provide a method of forming tip-corner-shaped floating gate oxide.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer. A floating gate oxide structure, comprising: (1) a structure having a dielectric layer thereover; (2) a patterned nitride layer over the dielectric layer; the patterned nitride layer including an opening therein proximate undercuts between the patterned nitride layer and the dielectric layer; (3) a floating gate oxide layer between the dielectric layer and the patterned nitride layer; the floating gate oxide layer including: opposing tip corners within the undercuts; and a central, bulge portion at least partially exposed by the patterned nitride layer opening.